The W682510 is a dual channel PCM CODEC with pin-selectable µ-Law or A-Law companding according to ITU G.711 and G.712. It has a built-in PLL which eliminates the need for a master clock. The analog section is fully differential, reducing noise and improving the power supply rejection ratio. The analog output is non-inverted. The device operates off a single +5V power supply and is available in PDIP-20, SOP-24 and SSOP-20 package options.
Diagram
Block Diagram
Application Diagram
Features
Single and Dual Channel devices available
PCM Encoding
A-Law/m-Law companding according to ITU-T G.711 by pin selection (except W681360)
13-bit Linear ADC/DAC conversion with 2s complement data format (W681360 only)
A/D & D/A filter according to ITU-T G.712
Lowest power dissipation in the industry in standby and powered modes
Extensive Master Clocks options (256kHz to 4800kHz)
PCM Digital Interface Clock Formats
Short Frame Sync
Long Frame Sync
IDL
GCI
Fully-Differential Analog Circuit Design for lowest noise
News & Events
