80C51 SMS Phone Microcontroller

Part No. W925EP01FG
Datasheet W925EP01_W925EP01FG.pdf
Description The W925EP01 is an all in one single 8-bit micro-controller with widely used Calling Identity Delivery (CID) function. The 8-bit CPU core is based on the 8051-family; therefore, all the instructions are compatible to the Turbo 8051 series.That contains a 64K bytes of main Flash EPROM (APROM) and a 4K bytes of auxiliary Flash EPROM (LDROM) which allows the contents of the 64KB main Flash EPROM (APROM) to be updated by the loader program located at the 4KB auxiliary Flash EPROM (LDROM). W925EP01 can be extend to two 64KB program banks, there are APROM (00000H~0FFFFH) and external program ROM (10000H~1FFFFH), user can access the external ROM by P5, P6, P7, A16 and . All instructions are fetched for execution from this memory areas, the MOVC instruction can also access the external memory regions. The CID part consisted of FSK decoder, DTMF receiver, CPE* Alert Signal (CAS) detector and Ring detector. Also are built-in DTMF generator, FSK generator with baud rate 1200 bps (bits/sec) and CAS generator. Using W925EP01 can easily implement the CID adjunct box and the feature phone or Short Message Service (SMS) phone with CID function. The main features are listed in the next section.
Features
  • CPU: 8-bit micro-controller is similar to the 8051 family.
    • Flash EPROM type (E version) operating voltage:
      μC: The μC operating voltage is from 2.4 to 5.5V. The ISP operating voltage is from 3.3 to 5.5V.
      CID: The CID receiver operating voltage is from 3.0 to 5.5V.
  • Dual-clock operation:
    • Main oscillator: Connect with 4M/8MHz crystal, built-in RC oscillator for clock stable from main crystal wake up.
    • Sub oscillator: connect with 32768Hz crystal.
    • Main and sub oscillators are enabled/disabled by bit control individually.
  • ROM:
    • 64K bytes of in-system-programmable Flash EPROM for application program (APROM).
    • 4K bytes of auxiliary Flash EPROM for loader program (LDROM).
    • 64K bytes external program memories address space.
  • RAM:
    • 256 bytes on chip scratch pad RAM.
    • 4K bytes on chip RAM for MOVX instruction.
    • 64K bytes external data memories address space.
  • CID
    • Compatible with Bellcore TR-NWT-000030 & SR-TSV-002476, British Telecom (BT) SIN227, U.K. Cable Communication Association (CCA) specification.
    • FSK modulator/demodulator: for Bell 202 and ITU-T V.23 FSK with 1200-baud rate.
    • CAS generator/detector: for dual tones of Bellcore CAS and BT Idle State and Loop State Dual Tone Alert Signal (DTAS).
    • DTMF generator/receiver; DTMF receiver can be programmed as a tone detector.
    • Ring detector: for line reversal for BT, ring burst for CCA or ring signal for Bellcore.
    • Two independent OP amps with adjustable gain for Tip/Ring and Telephone Hybrid connections.
      Note: ”CPE*” Customer Premises Equipment
  • I/O: 64 I/O pins.
    • P0: Bit and byte addressable. I/O mode can be bit controlled. Open drain type.
    • P1~P3: Bit and byte addressable. Pull high and I/O mode can be bit controlled.
    • P4: Byte addressable. Pull high and I/O mode can be bit controlled.
    • P5~P6: Byte addressable. Pull high and I/O mode can be bit controlled, P5~P6 also provide the address bus A0~A15 for access external program memory or data memory.
    • P7: Byte addressable. Pull high and I/O mode can be bit controlled, P7 also provide the data bus D0~D7 for access external program memory or data memory
  • Power mode:
    • Normal mode: Normal operation.
    • Dual-clock slow operation mode: System is operated from the sub-oscillator. (Fosc=Fs and Fm is stopped)
    • Idle mode: CPU hold. The clock to the CPU is halted, but the interrupt, timer and watchdog timer block work normally but CID function is disabled.
    • Power down mode: All activity is completely stopped and power consumption is less than 1uA.
  • Timer: Dual 13/16-bit timers or 8-bit auto-reload timers, that are Timer0 and Timer1.
  • Watchdog timer: WDT can be programmed by the user to serve as a system monitor.
  • Interrupt: 12 interrupt sources with two levels of priority.
    • 4 interrupts from INT0, INT1, INT2 and INT3.
    • 2 interrupts from Timer0 and Timer1.
    • 2 interrupt from Serial port0 and Serial port1.
    • 1 interrupt from CID.
    • 1 interrupt from 13/14-bit Divider.
    • 1 interrupt from Comparator.
    • 1 interrupt from Watch Dog Timer.
  • Divider: 13/14bit divider, clock source from sub-oscillator. Therefore, DIVF set every 0.25/0.5 second.
  • Comparator:
    • Comparator: 1 analog input from VNEG pin. 1 reference input from VPOS pin.
  • Serial ports:
    • Serial port0: One full duplex serial port. (UART)
    • Serial port1: An 8-bit serial transceiver with SCLK1 and SDATA1. (Serial interface port)
Diagram N/A
Package LQFP100 (Lead-Free RoHS)
Other Files N/A
Development Tools N/A
Others N/A

Contact us: MicroC-8bit@nuvoton.com