DDR Bus Termination Regulator

Part No.	W83312SN
Datasheet	W83312SN.pdf
Description	The W83312SN is a linear regulator which provides a power achieves peak 3.0Amp bi-directional sinking and sourcing capability for a high speed bus terminator application. The chip simply implements a stable power supply which tracks half of input power dynamically for bus terminator with a single chip. The W83312SN is promoted with small footprint 8-SOP 150mil power package. With W83312SN design, a high integration, high performance, and cost-effective solution are promoted.
Features	Memory Termination Regulator for DDR1, DDR2, DDR3 and Low Power DDR3 Sink and Source 3A Peak Current Integrated Power MOSFET Adjustable VOUT by External Resistors Low External Component Count Low Output Voltage Offset Current Limit Protection Over Temperature Protection
Diagram	N/A
Package	SOP-8 150mil with Exposed Pad, Lead Free (ROHS Compliant) and Halogen Free Package
Other Files	N/A
Development Tools	N/A
Others	N/A