DDR Bus Termination Regulator

Part No.	W83311SG
Datasheet	W83311SG.pdf
Description	The W83311SG is a linear regulator which provides a power achieves peak 3.0Amp bidirectional sinking and sourcing capability for a high speed bus terminator application. The chip simply implements a stable power supply which tracks half of input power dynamically for bus terminator with a single chip. The W83311SG is promoted with small footprint SOP-8 150mil power package. With W83311SG design, a high integration, high performance, and cost-effective solution are promoted.
Features	Support DDRI (1.25VTT), DDR2 (0.9VTT) and DDR3 (0.75VTT) Requirements Sink and Source Peak 3A Current/ Continuous 2.5A Current Integrated Power MOSFET Adjustable VOUT by External Resistors Low External Component Count Low Output Voltage Offset Short Circuit Protection 0ºC to 70ºC Ambient Operating Temperature Range SOP-8 (Exposed Pad) Package, Lead (Pb) Free
Diagram	N/A
Package	Power SOP 8
Other Files	N/A
Development Tools	N/A
Others	N/A