DDR Bus Termination Regulator

DDR bus termination regulator is a linear regulator for applications of a high speed bus terminator. The chip provides a stable power supply which tracks half of input power dynamically for bus termination with a single chip. The bus termination regulator is available in SOP-8, power SOP-8 and TO-252 packages. With DDR bus termination regulator design, a high integration, high performance, and a cost-effective solution are promoted.

Part No. Load Regulation Output Current Max Vin Control Voltage Protection Package Status* RoHS Datasheet
W83310G-R2
-20mV~+20mV
2 A
1.4V-3.6V
3V - 3.3V
OCP
SOP 8
P
Y
Available
W83310DG-A
-20mV~+20mV
2 A
1.4V-3.6V
3V - 3.3V
OCP
Power SOP 8
P
Y
Available
W83310DG
-20mV~+20mV
2 A
1.4V-3.6V
3V - 3.3V
OCP
Power SOP 8
P
Y
Available
W83310UG
-20mV~+20mV
2 A
1.4V-3.6V
3V - 3.3V
OCP,OTP
TO252
P
Y
Request
W83311SG
-20mV~+20mV
Peak 3A
1.4V-3.6V
3V - 3.3V
OCP
Power SOP 8
P
Y
Available
W83312SN
-20mV~+20mV
Peak 3A
1.2V-5.5V
3V - 5.5V
OCP,OTP
Power SOP 8
P
Y
Available

* Status: P= Mass Production, S=Samples, UD=Under Development, UD (Time)= Under Development(Ready Time), EOL=End of life.

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