Clock for SiS Chipsets

Part No.	W83176G-732
Datasheet	W83176G732.pdf
Description	The W83176G-732 is a 2.5V Zero-delay D.D.R. Clock buffer designed for SiS chipset, which can support 2 D.D.R. DRAM DIMMs, and provides I²C serial bus interface to program the registers to enable or disable each clock outputs. W83176G-732 accepts a reference clock as its input and runs on 2.5V supply.
Features	Zero-delay clock outputs Feedback pins for synchronous Supports up to 2 D.D.R. DIMMs One pairs of additional outputs for feedback Low Skew outputs (< 100ps) Supports 400MHz D.D.R. SDRAM I²C 2-Wire serial interface and supports Byte or Block Date RW
Diagram	N/A
Package	SSOP 28 Pb-free package
Other Files	N/A
Development Tools	N/A
Others	N/A