The
W682510 is a dual channel PCM CODEC with pin-selectable µ-Law or
A-Law companding according to ITU G.711 and G.712. It has a built-in PLL
which eliminates the need for a master clock. The analog section is fully
differential, reducing noise and improving the power supply rejection
ratio. The analog output is non-inverted.
The device operates off a single +5V power supply and is available in
PDIP-20, SOP-24 and SSOP-20 package options. |
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Related links |
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Block Diagram |
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Application Diagram |
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